Refine your search
Co-Authors
Journals
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Singh, Saurabh
- Analyzing the Financial Soundness of Public Sector Banks in India Using CAMEL Model
Abstract Views :224 |
PDF Views:1
Authors
Affiliations
1 College of Agribusiness Management, GBPUAT, Pantnagar, Udham Singh Nagar (Uttarakhand), IN
2 College of Agribusiness Management, GBPUAT, Udham Singh Nagar (Uttarakhand), IN
1 College of Agribusiness Management, GBPUAT, Pantnagar, Udham Singh Nagar (Uttarakhand), IN
2 College of Agribusiness Management, GBPUAT, Udham Singh Nagar (Uttarakhand), IN
Source
International Journal of Commerce & Business Management, Vol 11, No 1 (2018), Pagination: 1-11Abstract
The Indian banking system has undergone tremendous changes in the last decade, its financial soundness and performance being paramount in the achievement of a stable and sustainable economic growth. Thus, the aim of this research was to analyze the financial soundness of the public sector banks that operate in India. In order to achieve this, one of the most popular methods for the analysis of the financial soundness of banks namely CAMEL model was used. The obtained results highlight the strength and vulnerabilities of the analyzed banks underlying the need to strengthen the concerns of the decision makers from banks to improve and increase their soundness. The study concluded that the Punjab National Bank’s overall performance was very good followed by State Bank of India and the financial performance was very poor in case of IDBI.Keywords
CAMEL Model, Financial Soundness, Performance, Public Sector Banks.
References
- Annual Reports of Public Sector Banks, 2013-17.
- Evan, O., Leone, A.M., Gill, M. and Hilbers, P. (2000). Macro prudential indicators of financial system soundness, IMF Occasional paper, no.192.
- Hays, F., De Lurgio, S. and Gilbert, A. J. (2009). Efficiency ratios and community bank performance, J. Finance & Account., 1: 1.
- IMF and World Bank (2005). Financial sector assessment: A Handbook.
- Ishaq, A.B., Karim, A., Ahmed, S. and Zaheer, A. (2016). Evaluating performance of commercial banks in Pakistan: An Application of CAMEL model. J. Business & Financial Affairs, 5(1):1-30.
- Kumar, M. A., Harsha, G. S., Anand, S. and Dhruva, N. R. (2012). Analyzing soundness in Indian banking: A CAMEL approach. Res. J. Mgmt. Sci., 1(3) : 9-14.
- Master Circulars (2017). Prudential norms on capital adequacy, Reserve Bank of India.
- Roman, A. and Sargu, A.C. (2013). Analysing the financial soundness of the commercial banks in Romania: an approach based on the camels framework. Procedia Econ. & Finance 6 : 703-712.
- Shukla, Sneha S. (2015). Analyzing financial strength of Public and Private Sector Banks: A CAMEL approach. Pacific Business Rev. Internat., 7 (8) : 44-50.
- Trivedi, Apoorva, Rehman, Anisur and Elahi, Yasir Arafat (2015). A comparative analysis of performance of public and private sector banks in India through CAMEL rating system. Internat. J. Appl. Financial Mgmt. Perspectives, 4 (2) :1724-1736.
- Scenario Analysis of Different Social Media Platforms for Consumer Decision Making Process
Abstract Views :447 |
PDF Views:2
Authors
Affiliations
1 College of Agribusiness Management, G.B. Pant University of Agricuture and Technology, Pantnagar, U.S. Nagar (Uttarakhand), IN
1 College of Agribusiness Management, G.B. Pant University of Agricuture and Technology, Pantnagar, U.S. Nagar (Uttarakhand), IN
Source
International Journal of Commerce & Business Management, Vol 13, No 1 (2020), Pagination: 16-20Abstract
As social media is ubiquitous, its usage is growing rapidly. Social media has impacted the decision-making process of consumers. This research aims to do a scenario analysis of six social media platforms based on consumers’ preferences. It presents the consumers preferences during different stages of decision-making process. The selected platforms are Facebook, Twitter, LinkedIn, YouTube, Company Portal and Consumer Opinion Forums. These platforms are selected on the basis of their ranking on Alexa.com site. The study used datafrom 250 social media users of Delhi and responses are evaluated using descriptive statistics. The results depicted that consumers perceive different social media platform with different perspective and use different social media platforms for each stage of consumer decision making.Keywords
Consumer Decision Making Process, Scenario Analysis, Social Media, Social Media Platforms.References
- Bilal, G., Ahmed, M.A. and Shehzad, M.N. (2014). Role of social media and social networks in consumer decision making: A case of the garment sector. Internat. J. Multidisciplinary Sci. & Engg., 5(3) : 1-9.
- Engel, J.F., Kollat, D.T. and Blackwell, R.D. (1968). Consumer behavior. : Holt Rinehart and Winston, New York.
- Hennig-Thurau, T. and Walsh, G. (2003). Electronic word-of-mouth: motives for and consequences of reading customer articulations on the Internet. Internat. J. Electronic Commerce 8: 51–74.
- Kaur, K., Gnasigamoney, S.S. and Muthiah, S. (2014). The Influence of Social Media on the Consumer Decision Making Process Amongst University Students in Malaysia.
- Mishra, D., Narendra Kumar, N. and Sharma, A. (2012). Impact of online social media on consumer decision making: A study in Dehradun. Internat. J. Scientific Res., 3(5) : 379-381.
- Singla, N. and Arora, R. (2015). Social Media and Consumer Decision Making: A Study of University Students. Internat. J. Mktg. & Business Communication, 4(4) : 32-38.
- Occurrence of sapphirine-bearing granulites from Kothuru, Eastern Ghats Mobile Belt: implications on ultra-high temperature metamorphism
Abstract Views :166 |
PDF Views:93
Authors
Saurabh Singh
1,
Divya Prakash
1,
Chandra Kant Singh
1,
Vedika Srivastava
1,
Manoj Kumar Yadav
2,
Pradip Kumar Singh
1,
Manish Kumar
1
Affiliations
1 Centre of Advanced Study in Geology, Banaras Hindu University, Varanasi 221 005, IN
2 Centre of Advanced Study in Geology, Lucknow University, Lucknow 226 007, IN
1 Centre of Advanced Study in Geology, Banaras Hindu University, Varanasi 221 005, IN
2 Centre of Advanced Study in Geology, Lucknow University, Lucknow 226 007, IN
Source
Current Science, Vol 122, No 11 (2022), Pagination: 1298-1304Abstract
In this study, we present evidence for the stable coexistence of sapphirine + quartz and the compositional characteristics of the sapphirine-bearing granulites from Kothuru in the Eastern Ghats Mobile Belt (EGMB), India. The study area is an integral part of the Precambrian terrane in the western part of EGMB and is characterized by the granulite facies rocks comprising mainly of pelitic granulites such as charnockites, enderbites, leptynites, khondalites and gneisses, and sapphirine–spinel–quartz-bearing rocks. The chemistry of the minerals present in the assemblage has been examined using the electron probe micro analyser to infer their occurrence and distribution in various reaction textures observed during the petrographic study. The peak and post-peak history of the sapphirine-bearing granulites of Kothuru section have been constrained in the NCKFMASHTO system showing decompressional P–T path of high-grade metamorphic rocks through the intersection of the isopleth contours of various mineral phases present. The proposed P–T path with a steep isothermal decompression retrograde trajectory may be attributed to the over-thrust processes. The results obtained from the petrographic study of the mineral assemblages along with their textural relationship, mineral chemistry, especially Fe3+/FeTotal ratio and pseudosection modelling reveal that the studied segment has arrested promising ultra-high temperature metamorphic signatures and is tectonically distinct from those reported in the adjacent areas.Full Text
References
- Mukhopadhyay, D. and Basak, K., The Eastern Ghats belt – a polycyclic granulite terrain. J. Geol. Soc. India, 2009, 73, 489–518.
- Dasgupta, S., Bose, S. and Das, K., Tectonic evolution of the Eastern Ghats Belt, India. Precambrian Res., 2013, 227, 247–258.
- Das, K., Bose, S., Karmakar, S., Dunkley, D. J. and Dasgupta, S., Multiple tectonometamorphic imprints in the lower crust: first evidence of ca. 950 Ma (zircon U–Pb SHRIMP) compressional reworking of UHT aluminous granulites from the Eastern Ghats Belt, India. Geol. J., 2011, 46, 217–239.
- Korhonen, F. J., Brown, M., Clark, C. and Bhattacharya, S., Osumilite-melt interactions in ultrahigh temperature granulites: phase equilibria modelling and implications for the P–T–t evolution of the Eastern Ghats Province, India. J. Metamorph. Geol., 2013, 31, 881–907.
- Prakash, D., Singh, D., Singh, P. C., Singh, C. K., Tewari, S., Arima, M. and Frimmel, H. E., Reaction textures and metamorphic evolution of sapphirine–spinel-bearing and associated granulites from Diguva Sonaba, Eastern Ghats Mobile Belt, India. Geol. Mag., 2015, 152, 316–340.
- Harley, S. L., Refining the P–T records of UHT crustal metamorphism. J. Metamorph. Geol., 2008, 26, 125–154.
- Dharma Rao, C. V., Santosh, M. and Chmielowski, R. M., Sapphirine granulites from Panasapattu, Eastern Ghats Belt, India: ultrahigh-temperature metamorphism in a Proterozoic convergent plate margin. Geosci. Front., 2012, 3, 9–31.
- Ramakrishnan, M., Nanda, J. K. and Augustine, P. F., Geological evolution of the Proterozoic Eastern Ghats Mobile Belt. Geol. Surv. India, Spec. Publ., 1998, 44, 1–21.
- Dasgupta, S. and Sengupta, P., Indo-Antarctic correlation: a perspective from the Eastern Ghats Belt. Geol. Soc. London, Spec. Publ., 2003, 206, 131–143.
- Nanda, J. K. and Pati, U. C., Field relations and petrochemistry of the granulites and associated rocks in the Gnjam–Koraput sector of the Eastern Ghats Belt. Indian Miner., 1989, 43, 247–264.
- Schreyer, W., Maresch, W. V. and Daniels, P., Potassic cordierites: characteristic minerals for high-temperature, very low-pressure environments. Contr. Mineral. Petrol., 1990, 105, 162–172.
- Vry, J. K., Brown, P. E. and Valley, J. W., Cordierite volatile content and the role of CO2 in high-grade metamorphism. Am. Mineral.1990, 75, 71–88.
- Bose, S., Das, K. and Fukuoka, M., Fluorine content of biotite in granulite-grade metapelitic assemblages and its implications for the Eastern Ghats granulites. Eur. J. Mineral., 2005, 17, 665–674.
- Holland, T. J. B. and Powell, R., An internally-consistent thermodynamic dataset for phases of petrological interest. J. Metamorph. Geol., 1998, 16, 309–343.
- Holland, T. J. B. and Powell, R., An improved and extended internally consistent thermodynamic dataset for phases of petrological interest, involving a new equation of state for solids. J. Metamorph. Geol., 2011, 29, 333–383.
- Connolly, J. A. D., Multivariable phase-diagrams – an algorithm based on generalized thermodynamics. Am. J. Sci., 1990, 290, 666–718.
- Connolly, J. A. D., Computation of phase equilibria by linear programming: a tool for geodynamic modeling and its application to subduction zone decarbonation. Earth Planet. Sci. Lett., 2005, 236, 524–541.
- Connolly, J. A. D., The geodynamic equation of state: what and how. Geochem. Geophys. Geosyst., 2009, 10, 1–19.
- Connolly, J. A. D. and Petrini, K., An automated strategy for calculation of phase diagram sections and retrieval of rock properties as a function of physical conditions. J. Metamorph. Geol., 2002, 20, 697–708.
- Harley, S. L. and Hensen, B. J., Archaean and Proterozoic highgrade terranes of East Antarctica (40–80°E); a case study of diversity in granulite facies metamorphism. Mineral. Soc. Ser., 1990, 2, 320–370.
- Tamashiro, I., Santosh, M., Sajeev, K., Morimoto, T. and Tsunogae, T., Multistage orthopyroxene formation in ultrahigh-temperature granulites of Ganguvarpatti, southern India: implications for complex metamorphic evolution during Gondwana assembly. J. Mineral. Petrol. Sci., 2004, 99, 279–297.
- Tateishi, K., Tsunogae, T., Santosh, M. and Janardhan, A. S., First report of sapphirine + quartz assemblage from Southern India: implications for ultrahigh temperature metamorphism. Gondwana Res., 2004, 7, 899–912.
- Lal, R. K., Ackermand, D. and Upadhyay, H., P–T–X relationships deduced from corona textures in sapphirine–spinel–quartz assemblages from Paderu, southern India. J. Petrol., 1987, 28, 1139–1168.
- Santosh, M. and Kusky, T. M., Origin of paired high pressure–ultrahigh–temperature orogens: a ridge subduction and slab window model. Terra Nova, 2010, 22, 35–42.
- Hardware Security Model With Vedic Multiplier Based Ecc Algorithm On High-performance Fpga Device
Abstract Views :107 |
PDF Views:0
Authors
Saurabh Singh
1,
Sunita Soni
1
Affiliations
1 Department of Computer Science and Engineering, Bhilai Institute of Technology, IN
1 Department of Computer Science and Engineering, Bhilai Institute of Technology, IN
Source
ICTACT Journal on Microelectronics, Vol 8, No 1 (2022), Pagination: 1283-1287Abstract
The key problem that the world is most concerned about is security. Data security is the process of preventing unauthorized access to sensitive data. It includes all of the cybersecurity measures you take to keep your data safe from unauthorized access, such as encryption and access restrictions (both physical and digital). Data security has always been of the utmost importance. We utilize cryptographic methods to improve the services of data security. The application of cryptographic algorithms achieves data encryption. Therefore, we developed two versions of ECC algorithms on FPGA for improved hardware security in this study. The FPGA device employed here is Kintex-7, and there are two types of ECC: standard ECC and Vedic multiplier-based ECC. Vedic multiplier-based ECC has discovered that it consumes less space than standard ECC. Not only does Vedic multiplier-based ECC save space, but it also saves electricity. As a result, it is determined that for improved hardware security with ECC enabled, Vedic Multiplier-based ECC should be used over standard ECC.Keywords
ECC, Vedic Multiplier based ECC, Area, Power, and FPGAReferences
- Keshav Kumar, K.R. Ramkumar and Amanpreet Kaur, “A Lightweight AES Algorithm Implementation for Encrypting Voice Messages using Field Programmable Gate Arrays”, Journal of King Saud University-Computer and Information Sciences, Vol. 83, pp. 1-18, 2020.
- Aryan Kaushik and Keshav Kumar, “Design and Implementation of Advanced Encryption Standard Algorithm on 7th Series Field Programmable Gate Array”, Proceedings of International Conference on Smart Structures and Systems, pp. 1-3, 2020.
- Keshav Kumar, K.R. Ramkumar and Amanpreet Kaur, “A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA”, Proceedings of International Conference on Reliability, Infocom Technologies and Optimization, pp. 182-185, 2020.
- Keshav Kumar, K.R. Ramkumar and Amanpreet Kaur, “A Survey on Hardware Implementation of Cryptographic Algorithms Using Field Programmable Gate Array”, Proceedings of International Conference on Communication Systems and Network Technologies, pp. 189-194, 2020.
- K. Kumar, S. Malhotra and A. Kumar, “Design of Thermal-Aware and Power-Efficient LFSR on Different Nanometer Technology FPGA for Green Communication”, Proceedings of International Conference on Communication Systems and Network Technologies, pp. 236-240, 2021.
- K. Kumar, S. Malhotra and A. Kumar, 2019, "Frequency Scaling Based Low Power Oriya Unicode Reader (OUR) Design ON 40nm and 28nm FPGA”, International Journal of Recent Technology and Engineering, Vol. 7, No. 6, pp. 1-13, 2019.
- Bishwajeet Pandey, Keshav Kumar and Aiza Batool Shabeer Ahmad, “Implementation of Power-Efficient Control Unit on Ultra-Scale FPGA for Green Communication”, 3C Tecnologia, Vol. 10, No. 1, pp. 93-105, 2021.
- Bishwajeet Pandey and Keshav Kumar, “Leakage Power Consumption of Address Register Interfacing with Different Families of FPGA”, International Journal of InnovativeTechnology and Exploring Engineering, Vol. 9, No. 2, pp. 512-514, 2019.
- Keshav Kumar, Amanpreet Kaur, S.N. Panda, “Effect of Different Nano Meter Technology Based FPGA on Energy Efficient UART Design”, Proceedings of International Conference on Communication Systems and Network Technologies, pp. 1-4, 2018.
- C.T. Poomagal, G.A. Sathish Kumar and D. Mehta, “Revisiting the ECM-KEEM Protocol with Vedic Multiplier for Enhanced Speed on FPGA Platforms”, Journal of Ambient Intelligence and Humanized Computing, Vol. 98, pp. 1-11, 2021.
- R.K. Kadu and D.S. Adane, “Hardware Implementation of Efficient Elliptic Curve Scalar Multiplication using Vedic Multiplier”, International Journal of Communication Networks and Information Security, Vol. 11, No. 2, pp. 270-277, 2019.
- P. Ahuja, H. Soni and K. Bhavsar, “Fast, Secure and Efficient Vedic Approach for Cryptographic Implementations on FPGA”, Proceedings of International Conference on Electronics, Communication and Aerospace Technology, pp. 1706-1710, 2018.
- P. Ahuja, H. Soni and K. Bhavsar, “High Performance Vedic Approach for Data Security using Elliptic Curve Cryptography on FPGA”, Proceedings of International Conference on Trends in Electronics and Informatics, pp. 187-192, 2018.
- S. Karthikeyan and M. Jagadeeswari, “Performance Improvement of Elliptic Curve Cryptography System using Low Power, High Speed 16× 16 Vedic Multiplier based on Reversible Logic”, Journal of Ambient Intelligence and Humanized Computing, Vol. 12, No. 3, pp. 4161-4170, 2021.
- R.K. Kodali, S.S. Yenamachintala and L. Boppana, “FPGA Implementation of 160-Bit Vedic Multiplier”, Proceedings of International Conference on Devices, Circuits and Communications, pp. 1-5, 2014.
- T.S. Reddy and Y.D.S.Raju, “Implementation of Data Security with Wallace Tree Approach using Elliptical Curve Cryptography on FPGA”, Turkish Journal of Computer and Mathematics Education, Vol. 12, No. 6, pp. 1546-1553, 2021.
- Effect Of Adder Circuits Over Multiplier Design Based On Vedic Mathematics
Abstract Views :85 |
PDF Views:0
Authors
Saurabh Singh
1,
Sunita Soni
1
Affiliations
1 Department of Computer Science and Engineering, Bhilai Institute of Technology, IN
1 Department of Computer Science and Engineering, Bhilai Institute of Technology, IN
Source
ICTACT Journal on Microelectronics, Vol 7, No 4 (2022), Pagination: 1256-1259Abstract
Multiplication is critical for computers linked to cryptography or the ALU function. It consumes more chip area and time than the other ALU functions. The speed of the processor, coprocessor, or embedded system may depend on the multipliers’ speed. Nowadays, designing a small, high-performance multiplier is a critical challenge in computer architecture, cryptographic hardware design, and embedded system design. One of the better solutions is developing a digital multiplier design based on Vedic mathematical formula. The performance of the Digital Vedic Multiplier (DVM) is entirely dependent on the adder network. DVM is evaluated here using KS Adder and CLA Adder. There are several publications on this topic, but the primary shortcoming is that they focus exclusively on the DVM without addressing the influence of the adder circuit. This work aims to investigate the impact of the adder circuit on the space-speed trade-off inherent in the design of the DVM.Keywords
Vedic Mathematics, Digital Vedic Multiplier, Adder, Urdhv Triyagyabhyam, SpeedReferences
- S.B.K. Tirtha and V.S. Agrawala, “Vedic Mathematics”, Motilal Banarsidass Publishers Private Limited, 2013.
- S. Singh, “Design of High-Speed Multiplier using Ancient Indian”, Master Thesis, Department of Electronics, Chhattisgarh Swami Vivekanand Technical University, pp. 1-87, 2009.
- H. Thapliyal and M.B. Srinivas, “High Speed Efficient NxN Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematics”, Enformatika, Vol. 2, pp. 225-228, 2004.
- H. Thapliyal and H.R. Arabnia, “A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics”, Proceedings of International Conference on Embedded Systems and Applications, pp. 434-439, 2004.
- H. Thapliyal and M.B. Srinivas, “VLSI Implementation of RSA Encryption System using Ancient Indian Vedic Mathematics”, Proceedings of International Conference on Microtechnologies for the New Millennium, pp. 888-892, 2005.
- A. Singh, “Implementation of 16 Bit Vedic Multiplier”, Master Thesis, Department of Electrical and Electronics Engineering, Thapur University, pp. 1-72, 2010.
- R.K. Bathija, R.S. Meena, S. Sarkar and R. Sahu, “Low Power High Speed 16x16 bit Multiplier using VedicMathematics”, International Journal of Computer Applications, Vol. 59, No. 6, pp. 41-44, 2012.
- M. Pradhan, R. Panda and S.K. Sahu, “Speed Comparison of 16x16 Vedic Multipliers”, International Journal of Computer Applications, Vol. 21, No. 6, pp. 1-14, 2011.
- C. Venkatesan and P. Karthigaikumar, “An Efficient Noise Removal Technique using Modified Error Normalized LMS Algorithm”, National Academy Science Letters, Vol. 41, No. 3, pp. 155-159, 2018.
- S. Kannan, C. Selvaraj and S.N. Mohanty, “Forecasting Energy Generation in Large Photovoltaic Plants using Radial Belief Neural Network”, Sustainable Computing: Informatics and Systems, Vol. 34, No. 2, pp. 1-17, 2021.
- A.R. Suhas and M.M. Priyatham, “Heal Nodes Specification Improvement using Modified Chef Method for Group Based Detection Point Network”, International Journal of Pervasive Computing and Communications, Vol. 33, No. 2, pp. 1-12, 2021.
- M. Ramkumar, R. Manikandan, K.S. Kumar and R.K. Kumar, “Intrusion Detection in Manets using Support Vector Machine with Ant Colony Optimization”, ICTACT Journals on Data Science and Machine Learning, Vol. 1, No. 1, pp. pp. 37-42, 2019.
- Y. Bansal, C. Madhu and P. Kaur, “High Speed Vedic Multiplier Designs - A Review”, Recent Advances in Engineering and Computational Sciences, Vol. 2014, pp. 16, 2014.
- S. Akhter, “VHDL Implementation of Fast NxN Multiplier based on Vedic Mathematic”, Proceedings of International Conference on Circuit Theory and Design, pp. 472-475, 2007.
- R. Pushpangadan, V. Sukumaran and V. Sundar, “High Speed Vedic Multiplier for Digital Signal Processors”, IETE Journal of Research, Vol. 55, No. 6, pp. 282-286, 2009.
- A. Kanhe, S.K. Das and A.K. Singh, “Design and Implementation of Floating Point Multiplier based on Vedic Multiplication Technique”, Proceedings of International Conference on Communication, Information and Computing Technology, pp. 1-4, 2012.
- V. Kunchigik, L. Kulkarni and S. Kulkarni, “Pipelined Vedic-Array Multiplier Architecture”, International Journal of Image, Graphics and Signal Processing, Vol. 6, No. 6, pp. 58-67, 2014.
- T. Karthikeyan, K. Praghash and K.H. Reddy, “Binary Flower Pollination (BFP) Approach to Handle the Dynamic Networking Conditions to Deliver Uninterrupted Connectivity”, Wireless Personal Communications, Vol. 121, No. 4, pp. 3383-3402, 2021.
- S. Srimani, D.K. Kundu, S. Panda and B. Maji, “Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra”, Proceedings of International Conference on ComputationalAdvancement in Communication Circuits and Systems, pp. 443-449, 2015.
- S. Srimani, D.K. Kundu, S. Panda and B. Maji, “Implementation of Optimized High Performance 4x4 Multiplier using Ancient Vedic Sutra in 45 nm Technology”, Proceedings of International Conference on Devices, Circuits and Systems, pp. 1-6, 2014.
- K.B. Jagannatha, H.S. Lakshmisagar and G.R. Bhaskar, “FPGA and ASIC Implementation of 16-Bit Vedic Multiplier Using Urdhva Triyakbhyam Sutra”, Proceedings of International Conference on Emerging Research in Electronics, Computer Science and Technology, pp. 31-38, 2014.
- H. Sharma, G.K. Jindal, and P.R. Murthy, “Comparison Between Array Multiplier and Vedic Multiplier”, International Journal of Electronics and Communication Engineering and Technology, Vol. 8, No. 3, pp. 1-14, 2014.
- M. Pradhan and R. Panda, “High Speed Multiplier using Nikhilam Sutra Algorithm of Vedic Mathematics”, International Journal of Electronics, Vol. 101, No. 3, pp. 300-307, 2014.
- A. Tiwari and S. Lal, “An Approach Towards the HighEfficient and low Propagation Delay in Digital Processor”, International Journal of Electrical, Electronics and Computer Engineering, Vol. 6, No. 1, pp. 62-70, 2017.
- J. Kumar, K. Selva, and R. Rahim, “Design and UVM Verification of High Speed ALU”, International Journal on Emerging Technologies, Vol. 10, No. 1, pp. 93-96, 2019.
- G.G. Kumar and V. Charishma, “Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques”, International Journal of Scientific and Research Publications, Vol. 2, No. 3, pp. 1-15, 2012.
- R. Santhiya and M.T. Thamaraimanalan, “Power Gating Based Low Power 32 Bit BCD Adder using DVT”, International Journal for Scientific Research and Development, Vol. 3, No. 2, pp. 802-805, 2015.
- R.K. Kodali, S.S. Yenamachintala and L. Boppana, “FPGA Implementation of 160-Bit Vedic Multiplier”, Proceedings of International Conference on Devices, Circuits and Communications, pp. 1-5, 2014.
- C.Venkatesan, P. Karthigaikumar, A. Paul, S. Satheeskumaran and R. Kumar, “ECG Signal Preprocessing and SVM Classifier-Based Abnormality Detection in Remote Healthcare Applications”, IEEE Access, Vol. 6, pp. 9767-9773, 2018.
- K. Praghash and T. Karthikeyan, “An Investigation of Garbage Disposal Electric Vehicles (GDEVs) Integrated with Deep Neural Networking (DNN) and Intelligent Transportation System (ITS) in Smart City Management System (SCMS)”, Wireless Personal Communications, Vol. 124, No. 2, pp. 1-20, 2021